125 lines
6.2 KiB
JSON
125 lines
6.2 KiB
JSON
{
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"dataType": "CVE_RECORD",
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"dataVersion": "5.2",
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"cveMetadata": {
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"cveId": "CVE-2026-11985",
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"assignerOrgId": "e2e69745-5e70-4e92-8431-deb5529a81ad",
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"state": "PUBLISHED",
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"assignerShortName": "zephyr",
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"dateReserved": "2026-06-11T14:04:09.251Z",
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"datePublished": "2026-08-11T04:56:59.359Z",
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"dateUpdated": "2026-08-31T23:13:18.528Z"
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},
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"containers": {
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"cna": {
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"providerMetadata": {
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"orgId": "e2e69745-5e70-4e92-8431-deb5529a81ad",
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"shortName": "zephyr",
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"dateUpdated": "2026-08-31T23:13:18.528Z"
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},
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"title": "Cross-thread FPU register leak on ARM when FPU enabled without register sharing",
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"descriptions": [
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{
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"lang": "en",
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"value": "On the Zephyr ARM port, enabling the hardware FPU (CONFIG_FPU) forces the \"Floating point ABI\" choice, which defaults to CONFIG_FP_HARDABI. Both FP_HARDABI and FP_SOFTABI permit the compiler to emit hardware FP instructions in any function, even code that never uses floating-point types. However, the callee-saved FP registers (s16-s31 / d8-d15) are only saved and restored across a context switch when CONFIG_FPU_SHARING is enabled (arch/arm/core/cortex_m/swap_helper.S and arch/arm/core/cortex_a_r/swap_helper.S), and prior to this fix selecting an ABI did not enable FPU register sharing, which defaults off.\n\nIn a build that enables the FPU with the default ABI but leaves CONFIG_FPU_SHARING disabled, the kernel preserves no callee-saved FP register state across thread switches. The documented precondition for this \"unshared\" mode — that only a single thread ever executes FP instructions — is silently violated because the compiler may generate FP instructions in every thread.\n\nUnder CONFIG_USERSPACE, where threads are mutually isolated, this becomes an information-disclosure boundary crossing: a victim thread can leave secret-derived values in s16-s31, and a co-resident unprivileged thread can read those registers directly (FP register access is not privilege-gated), recovering data left behind by another thread. Without userspace the same defect causes cross-thread FP state corruption (a correctness fault). The leak is bounded to the 16 callee-saved single-precision registers and is opportunistic, so impact is low.\n\nThe fix makes FP_HARDABI and FP_SOFTABI select CONFIG_FPU_SHARING and tags every thread with K_FP_REGS at creation, so callee-saved FP state is always preserved across context switches whenever the compiler may emit FP instructions."
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}
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],
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"affected": [
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{
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"vendor": "zephyrproject",
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"product": "zephyr",
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"collectionURL": "https://github.com/zephyrproject-rtos/zephyr",
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"packageName": "zephyr",
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"defaultStatus": "unaffected",
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"programFiles": [
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"arch/Kconfig",
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"arch/arm/core/Kconfig",
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"arch/arm/core/cortex_a_r/thread.c",
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"arch/arm/core/cortex_m/thread.c"
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],
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"versions": [
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{
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"version": "1.13.0",
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"status": "affected",
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"versionType": "semver",
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"lessThan": "4.4.2"
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}
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]
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}
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],
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"references": [
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{
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"url": "https://github.com/zephyrproject-rtos/zephyr/commit/3d405326a7653cba6860280e45c8734f8d3fc423",
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"name": "Fix commit",
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"tags": [
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"patch"
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]
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},
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{
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"url": "https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-qxr9-wh3c-hvgv",
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"name": "GHSA-qxr9-wh3c-hvgv"
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}
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],
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"metrics": [
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{
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"format": "CVSS",
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"cvssV3_1": {
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"version": "3.1",
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"vectorString": "CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:L/I:L/A:N",
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"baseScore": 3.6,
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"baseSeverity": "LOW"
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}
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}
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],
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"problemTypes": [
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{
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"descriptions": [
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{
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"lang": "en",
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"description": "info-leak",
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"cweId": "CWE-200",
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"type": "CWE"
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}
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]
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}
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],
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"x_generator": {
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"engine": "cvelib 1.8.0"
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}
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},
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"adp": [
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{
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"metrics": [
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{
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"other": {
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"type": "ssvc",
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"content": {
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"timestamp": "2026-08-11T17:55:04.091131Z",
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"id": "CVE-2026-11985",
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"options": [
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{
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"Exploitation": "none"
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},
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{
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"Automatable": "no"
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},
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{
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"Technical Impact": "partial"
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}
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],
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"role": "CISA Coordinator",
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"version": "2.0.3"
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}
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}
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}
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],
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"title": "CISA ADP Vulnrichment",
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"providerMetadata": {
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"orgId": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
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"shortName": "CISA-ADP",
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"dateUpdated": "2026-08-11T17:55:22.188Z"
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}
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}
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]
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}
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} |